Dual-port DRAM cell with simultaneous access

ABSTRACT

A dual-port memory substantially eliminates noise problems associated with the staggered methods of operation. The first and second word lines of a dual-port memory cell are simultaneously activated, such that all four bit lines associated with the cell also move at the same time. The dual-port memory uses simple control logic circuitry without the need for additional external control signals. There are no lock-out times or write restrictions with the method of the present invention. The dual-port memory of the present invention includes a method for hiding refresh, and a method for increasing operating speed.

BACKGROUND OF THE INVENTION

The present invention relates, in general, to the field of integratedcircuit memories. More particularly, the present invention relates to adual-port integrated circuit memory architecture and method ofoperation.

A standard single-port or “1T/1C” DRAM cell 10 is shown in FIG. 1. DRAMcell 10 includes a pass transistor 18 and storage capacitor 22. Cell 10further includes a word line 16 coupled to the gate of transistor 18, aswell as a bit line 12 and complementary bit line 14. Bit line 12 iscoupled to the drain of transistor 18, and complementary bit line 14 iscoupled to the drain of transistors in other 1T/1C cells in an array ofcells (not shown in FIG. 1).

A standard dual-port or “2T/1C” DRAM cell 20 is shown in FIG. 2. DRAMcell 20 includes two pass transistors 34 and 36 each coupled to storagecapacitor 38. Cell 20 further includes a word line 42 coupled to thegate of transistor 34, and an additional word line 44 coupled to thegate of transistor 36. Cell 20 also includes a set of two bit lines 24and 28, as well as two complementary bit lines 26 and 32. Bit line 24 iscoupled to the drain of transistor 34 and bit line 28 is coupled to thedrain of transistor 36. Complementary bit lines 26 and 32 are coupled tothe drains of transistors in other 2T/1C cells in an array of cells(best seen in FIG. 3). Bit lines 24 and 26 and word line 42 areassociated with port A. Bit lines 28 and 32 are associated with a secondport and method for accessing the cell referred to as port B.

Referring now to FIG. 3, a portion 30 of an array of 2T/1C memory cellsis shown. The array portion 30 includes two rows and three columns ofcells in order to show the bit line and word line connections. In thefirst row of cells, cells 20A and 20C are connected to the two bit linesin the first set of bit lines 46. Cell 20B is connected to the twocomplementary bit lines in the first set of bit lines 46. In the secondrow of cells, cells 20D and 20F are connected to the two bit lines inthe second set of bit lines 48. Cell 20E is connected to the twocomplementary bit lines in the second set of bit lines 48. A first setof two word lines is coupled to a first column of cells that includescells 20A and 20D, a second set of two word lines is coupled to a secondcolumn of cells that includes cells 20B and 20E, and a third set of twoword lines is coupled to a third column of cells that includes cells 20Cand 20F. The interconnection pattern shown in FIG. 3 is extended asrequired to accommodate the number of rows and columns of cells in theentire array.

The standard DRAM cell 10 shown in FIG. 1 operates according to asimultaneous access method in which disturb problems between cells inthe array are minimized. However, many prior art techniques use astaggered access method for operating the dual-port DRAM cell 20 shownin FIG. 2 for refresh or read/write operations. This type of access canlead to noise problems and data disturbs, whereby some memory cells arebeing sensed while others in the same sub-array are being restored,causing noise between sets of memory cells.

Referring now to FIG. 4, a portion 40 of a dual-port 2T/2C memory arrayis shown in greater detail. In particular, sense amplifiers 52, 54, 56,and 58 are shown for resolving the data state of a pair of bit lines.The actual physical location of the sense amplifiers 52-58 in theintegrated circuit may be different from that shown in FIG. 4. Inaddition, FIG. 4 shows parasitic capacitors 53, 55, and 57 that can actas signal paths for undesirably affecting the data state of a selectedmemory cell or bit line in the array.

The disturb problem for a staggered access of a dual-port memory arrayis shown in greater detail in the timing diagram 50 of FIG. 5. The wordline signal 62 is shown for accessing the first port of the memory. Theword line signal 64 is also shown for accessing the second port of thememory, which is delayed in time by one-half of a clock cycle. The bitline waveforms 66 and 68 are shown for the first port. The bit linewaveforms include a first portion in which the bit line signal isdeveloped, and a second portion in which the bit line signal is resolvedby the sense amplifiers. The bit lines waveforms 72 and 74 are delayedby one-half of a clock cycle in response to the word line waveforms.This type of consecutive access to the dual-port cell can lead todisturb problems. A critical sensing time 76 occurs when a bit linesignal for the first port of the memory is being resolved when a bitline signal is being developed for the second port of the memory. Thelarge bit line signal on the first port can undesirably affect the datastate of the developing signal on the second port, which does notnormally occur for single port memories using simultaneous access.

What is desired, therefore, is a simple and cost effective dual-portmemory architecture and method of operation that eliminates the disturbproblems associated with the prior art staggered method of operating adual-port memory.

SUMMARY OF THE INVENTION

According to the present invention an architecture and method ofoperation for a dual-port memory substantially eliminates the noiseproblems associated with the known staggered methods of operation. Thearchitecture and method of operation of the dual-port memory of thepresent invention has substantially the same immunity to disturb andnoise problems as that found in conventional 1T/1C single-port DRAMswidely used today.

In a preferred method of operation, the first and second word lines of adual-port memory cell are activated at the same time, such that all fourbit lines associated with the cell also move at the same time. This thenconfers the same noise immunity as a conventional 1T/1C DRAM where allthe cells are sensed at the same time along a single word line in agiven sub-array, and disturb problems are minimized.

The dual-port memory of the present invention uses simple control logiccircuitry without the need for additional external control signals.There are no lock-out times or write restrictions with the method of thepresent invention as are found in prior art designs.

The dual-port memory of the present invention includes a firstembodiment for hiding refresh, and a second embodiment for increasingoperating speed.

In the first embodiment for hiding refresh, port A is used to read orwrite to the memory cell. Port B is used for refresh. An on-chip addressgenerator is used together with a refresh timer to generate the refreshaddress. The refresh address, if required, and the read/write addressare compared. If they are different, they are applied to the rowdecoders at the same time so that the word line on port A and the wordline on port B to different cells will be activated at the exact sametime. If the refresh address and read/write address are the same, thenno refresh is required and the word line on port B is inactive.

Word line B, therefore, is allowed to go high only if the word lineaddress is different from the word line A address. If they are the samethe cell has been refreshed by word line A. If both word line A and wordline B go high in the same cell, the bit line signal is cut in half, andonly one of the ports is activated.

The comparison of the word line A and word line B addresses can be doneduring the address setup time of the memory and does not materiallyimpact overall operating speed.

In the second embodiment, the two ports of the memory cell can beoperated to substantially increase operating speed. In the case of thedual-port memory, operating speed is effectively doubled. In thisembodiment, external addresses come into the memory at twice the rate ofthe word line cycle rate. Latency is used to compare the high speedaddressing so that if two consecutive word line addresses are the same,only one of the ports of the dual port cell is selected. If the twoaddresses are different, both port A and port B word lines go activesimultaneously, and data can be read or written into the selected cells.

Clock latency allows two consecutive row addresses to be compared. Ifthe addresses are different, port A and B of the memory are used atone-half rate. If they are the same, then only port A is used. Data canbe written and read at full rate. Internal word line or RAS cycle timescan run at a relaxed half-rate with the method of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The aforementioned and other features and objects of the presentinvention and the manner of attaining them will become more apparent andthe invention itself will be best understood by reference to thefollowing description of a preferred embodiment taken in conjunctionwith the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of a prior art single-port memory cell;

FIG. 2 is a schematic diagram of a prior art two-port memory cell;

FIG. 3 is a schematic diagram of a portion of a prior art two-portmemory cell array;

FIG. 4 is a schematic diagram of the memory cell array portion of FIG. 3further including sense amplifiers and parasitic capacitance;

FIG. 5 is a timing diagram showing various waveforms in a prior artstaggered method of operating a two-port memory;

FIG. 6 is a block diagram of a first embodiment of a dual-port memoryaccording to the present invention;

FIG. 7 is a timing diagram associated with the dual-port memory of FIG.6;

FIG. 8 is a block diagram of a second embodiment of a dual-port memoryaccording to the present invention; and

FIG. 9 is a timing diagram associated with the dual-port memory of FIG.8.

DETAILED DESCRIPTION

Referring now to FIG. 6, an integrated circuit memory 60 includes anarray of dual-port memory cells 78 including first and second word linebuses WLA and WLB, an address generator 92 for generating read/writeaddresses in response to addresses received on an external address bus,a refresh timer 88, a refresh address generator 84 having an inputcoupled to the refresh timer 88 and an output for generating refreshaddresses, a comparator 86 for comparing the read/write addresses to therefresh addresses, and a row decoder 82 having an input coupled to thecomparator 86, and first and second outputs for selectively driving thefirst and second word line buses WLA and WLB in response to the datastate of the comparator 86. A logic control block 93 is also shown inFIG. 6. Logic control block receives the CLOCK and COMMAND signals, andprovides a control signal output coupled to address generator 92. TheWLA and WLB word line buses have a width of 64, 128, or 256 bits,although other widths can be used. The memory cells in memory array 78are of the type shown in previous FIGS. 2 and 3.

The method of operating memory 60 includes reading or writing to a firstport (A) of the dual-port memory cells in the array 78, refreshing at asecond port (B) of the dual-port memory cells in the array, comparing aread/write address to a refresh address, and, if the read/write addressand the refresh address are different, simultaneously activating a wordline associated with the first port (A) of a first dual-port memory celland a word line associated with the second port (B) of a seconddual-port memory cell. For example, in FIG. 3, two different two-portmemory cells could be memory cell 20A and memory cell 20B.

If the read/write address and the refresh address are the same, thenonly the word line associated with the first port (A) of the selecteddual-port memory is activated. For example, in FIG. 3, only word lineWLA for memory cell 20A is activated.

In the method of the present invention, comparing the read/write andrefresh address can occur during a memory setup time so that memoryspeed is unaffected.

The method of the present invention is explained in further detail withrespect to the timing diagram of FIG. 7. The clock signal for the memory94 is shown in conjunction with four separate word line signals 96, 98,102, and 104 for different memory cells. Note that the first and secondport word line signals are always simultaneously activated. Word linesignals 96 and 98 are associated with a first memory cycle and word linesignals 102 and 104 are associated with a second memory cycle.

Referring now to FIG. 8, an integrated circuit memory 80 includes anarray of dual-port memory cells 78 including first and second word linebuses WLA and WLB, an address generator 92 for generating read/writeaddresses, a first FIFO 106 having an input coupled to the addressgenerator 92 and first and second outputs, a second FIFO 108 having aninput coupled to the first output of the first FIFO 106 and an output, acomparator 86 for comparing the second output of the first FIFO 106 tothe output of the second FIFO 108, and a row decoder 82 having an inputcoupled to the comparator 86, and first and second outputs forselectively driving the first and second word line buses WLA and WLB inresponse to the data state of the comparator 86. A logic control block93 is coupled to the address generator 92 and receives the CLOCK andCOMMAND inputs signals. In memory 80, the first FIFO 106 provides aone-half clock cycle delay between the input and each of the first andsecond outputs. The second FIFO 108 also provides a one-half clock cycledelay between the input and the output. An I/O buffer 95 is also shownin FIG. 8, for receiving data input signal 128 and for providing thedata output signal 130.

The method of operating memory 80 according to the present inventionincludes comparing a first read/write address to a second consecutiverefresh address, and, if the first and second read/write addresses aredifferent, simultaneously activating a word line associated with a firstport (A) of a first dual-port memory cell and a word line associatedwith a second port (B) of a second dual-port memory cell. For example,in FIG. 3, two different two-port memory cells could be memory cell 20Aand memory cell 20B.

If the first and second read/write addresses are the same, then only theword line associated with one of the ports of the selected dual-portmemory is activated. For example, in FIG. 3, only word line WLA formemory cell 20A is activated.

The method of the present invention uses a latency of three to comparethe first and second consecutive read/write addresses so that memoryspeed is unaffected. The effective improvement in the memory speed forthe dual-port memory 80 shown in FIG. 8 is about a factor of two.

The method of the present invention is explained in further detail withrespect to the timing diagram of FIG. 9. Timing diagram 90 includes amemory CLOCK signal 110. The ADDRESS and COMMAND buses 112 and 114 areshown. The ADDRESS bus includes the external addresses and the COMMANDbus includes information to request a READ, a WRITE or a NOP (nooperation). One standard COMMAND bus includes decoded /CE and /WEsignals. Another standard COMMAND bus includes /RAS, /CAS, and /WEsignals. Four word line signals 116, 118, 120, and 122 are shown.Signals 116 and 118 illustrate the activation of word line signals fordifferent memory cells in the array in the case of different consecutiveread/write addresses, in this case two consecutive reads on addresseszero (0) and then one (1). Note that word line signal 116 is foractivating the first port of a first memory cell with address zero (0)and word line signal 118 is for activating the second port of a secondmemory cell with address one (1). In contrast, word line signals 120 and122 illustrate the activation of a signal word line signal for the sameconsecutive read/write address two (2). Note that only the first portword line signal 120 is activated, whereas the second port word linesignal 122 remains inactive. Since the DIN, D2A, and D2B data word allcorrespond to the same address, only one word line needs to be selectedand the second data word D2B is written into the cell. If both wordlines are selected at the same time on the same for back-to-back reads,a failure would occur. The effective “half-charge”, since one cellcapacitor is used for sets of bit lines, results in a failure to sensethe correct data.

The clock latency periods 124 and 126 are shown for the first and secondaddress comparisons. Note that a latency of three is used, because theread request is pipelined in serially into FIFOs 106 and 108, performedin parallel in array 78, and then pipelined out serially through I/Obuffer 95.

Finally, the DIN data input signal 128 is received and the Q data outputsignal 130 is provided by I/O buffer 95.

While there have been described above the principles of the presentinvention in conjunction with specific memory architectures and methodsof operation, it is to be clearly understood that the foregoingdescription is made only by way of example and not as a limitation tothe scope of the invention. Particularly, it is recognized that theteachings of the foregoing disclosure will suggest other modificationsto those persons skilled in the relevant art. Such modifications mayinvolve other features which are already known per se and which may beused instead of or in addition to features already described herein.Although claims have been formulated in this application to particularcombinations of features, it should be understood that the scope of thedisclosure herein also includes any novel feature or any novelcombination of features disclosed either explicitly or implicitly or anygeneralization or modification thereof which would be apparent topersons skilled in the relevant art, whether or not such relates to thesame invention as presently claimed in any claim and whether or not itmitigates any or all of the same technical problems as confronted by thepresent invention. The applicants hereby reserve the right to formulatenew claims to such features and/or combinations of such features duringthe prosecution of the present application or of any further applicationderived therefrom.

1. A method of operating an array of dual-port memory cells comprising:reading or writing to a first port of the dual-port memory cells in thearray; refreshing at a second port of the dual-port memory cells in thearray; comparing a read/write address to a refresh address; and if theread/write address and the refresh address are different, simultaneouslyactivating a word line associated with the first port of a firstdual-port memory cell and a word line associated with the second port ofa second dual-port memory cell.
 2. The method of claim 1 furthercomprising, if the read/write address and the refresh address are thesame, then activating only the word line associated with the first portof the selected dual-port memory.
 3. The method of claim 1 furthercomprising comparing the read/write and refresh address during a memorysetup time so that memory speed is unaffected.
 4. An integrated circuitmemory comprising: an array of dual-port memory cells including firstand second word line buses; a refresh timer; a refresh address generatorhaving an input coupled to the refresh timer and an output for generatorrefresh addresses; a comparator for comparing the read/write address tothe refresh address; and a row decoder having an input coupled to thecomparator, and first and second outputs for selectively driving thefirst and second word line buses in response to the data state of thecomparator.
 5. The integrated circuit memory of claim 4 furthercomprising means for simultaneously activating a word line associatedwith a first port of a first dual-port memory cell and a word lineassociated with a second port of a second dual-port memory cell if theread/write address and the refresh address are different.
 6. Theintegrated circuit memory of claim 4 further comprising means foractivating only the word line associated with a first port of a selecteddual-port memory if the read/write address and the refresh address arethe same.
 7. The integrated circuit of claim 4 further comprising meansfor comparing the read/write and refresh addresses during a memory setuptime so that memory speed is unaffected.
 8. The integrated circuit ofclaim 4 in which the first word line bus comprises a 64, 128, or 256wide group of word lines.
 9. The integrated circuit of claim 4 in whichthe second word line bus comprises a 64, 128, or 256 wide group of wordlines.
 10. The integrated circuit of claim 4 in which the dual-portmemory array further comprises a first complementary bit line, a firstbit line, a second complementary bit line, and a second bit line.
 11. Amethod of operating an array of dual-port memory cells comprising:comparing a first read/write address to a refresh address; and if theread/write address and refresh address are different, simultaneouslyactivating a word line associated with a first port of a first dual-portmemory cell and a word line associated with a second port of a seconddual-port memory cell.
 12. The method of claim 11 further comprising, ifthe read/write address and the refresh address are the same, thenactivating only the word line associated with one of the ports of theselected dual-port memory.
 13. The method of claim 11 further comprisingusing latency to compare the first read/write address and the refreshaddress so that memory speed is unaffected.
 14. An integrated circuitmemory comprising: an array of dual-port memory cells including firstand second word line buses; a first FIFO having an input coupled to theaddress buffer and first and second outputs; a second FIFO having aninput coupled to the first output of the first FIFO and an output; acomparator for comparing the second output of the first FIFO to theoutput of the second FIFO; and a row decoder having an input coupled tothe comparator, and first and second outputs for selectively driving thefirst and second word line buses in response to the data state of thecomparator.
 15. The integrated circuit memory of claim 14 furthercomprising means for simultaneously activating a word line associatedwith a first port of a first dual-port memory cell and a word lineassociated with a second port of a second dual-port memory cell if firstand second read/write addresses are provided by the first and secondFIFOs are different.
 16. The integrated circuit memory of claim 14further comprising means for activating only the word line associatedwith one of the ports of the selected dual-port memory if first andsecond read/write addresses provided by the first and second FIFOs arethe same.
 17. The integrated circuit memory of claim 14 in which thefirst FIFO provides a one-half clock cycle delay between the input andeach of the first and second outputs.
 18. The integrated circuit memoryof claim 14 in which the second FIFO provides a one-half clock cycledelay.
 19. The integrated circuit of claim 14 in which the first wordline bus comprises a 64, 128, or 256 wide group of word lines.
 20. Theintegrated circuit of claim 14 in which the second word line buscomprises a 64, 128, or 256 wide group of word lines.